1. Technical Field
The present invention relates generally to memory management in processing systems, and more particularly, to a memory management scheme that provides reduction in memory array power consumption within a processing system when used in conjunction with a memory device power management scheme.
2. Description of the Related Art
Present-day computing systems include sophisticated power-management schemes for a variety of reasons. For portable computers such as “notebook”, “laptop” and other portable units including personal digital assistants (PDAs), the primary power source is battery power. Intelligent power management extends battery life, and therefore the amount of time that a user can operate the system without connecting to a secondary source of power. Power management has also been implemented over “green systems” concerns so that power dissipated within a building is reduced for reasons of energy conservation and heat reduction.
Recently, power management has become a requirement in line power connected systems, particularly high processing power cores and systems because the components and/or systems are now designed with total potential power consumption levels that either exceed power dissipation limits of individual integrated circuits or cabinets, or the total available power supply is not designed to be adequate for operation of all units simultaneously. For example, a processor may be designed with multiple execution units that cannot all operate simultaneously due to either an excessive power dissipation level or a problem in distributing the requisite current level throughout the processor without excessive voltage drop.
The above-incorporated U.S. Patent Applications “METHOD AND SYSTEM FOR POWER MANAGEMENT INCLUDING DEVICE CONTROLLER-BASED DEVICE USE EVALUATION AND POWER-STATE CONTROL” and “METHOD AND SYSTEM FOR POWER MANAGEMENT INCLUDING LOCAL BOUNDING OF DEVICE GROUP POWER CONSUMPTION” provide implementations of power management schemes for memory and other devices that can reduce the power consumed by a processing system, either by direction, or when devices in the system are infrequently used.
However, in many processing system applications, the amount of power saved will be minimal, as all of the memory devices may be active or be continuously entering and leaving a power-saving state other than the lowest power state available for most of the time the processing system is operating. The lowest power state may not even be reached by any of the memory devices during periods of high system activity if entry to the power saving states is controlled by a timer, as in the power-management control technique above-incorporated U.S. Patent Application “METHOD AND SYSTEM FOR POWER MANAGEMENT INCLUDING DEVICE CONTROLLER-BASED DEVICE USE EVALUATION AND POWER-STATE CONTROL”.
It is therefore desirable to provide a method and system for decreasing power consumption in a memory array of a processing system, wherein lower power consumption states form a greater portion of the overall power management state of the memory array over total system operating time.